Big PLD-Glossary

A   B   C   D   E   F   G   H   I   J   K   L   N   M   O   P   Q   R   S   T   U   V   W   X   Y   Z  A ABEL Advanced Boolean Expression Language - pioneer HDL of EDA-tools for digital systems (since 1983, introduced by "Data I/O Corporation", sometimes abbreviated with Abel-HDL, XABEL for Xilinx-ABEL) ADC Analog-to-Digital Converter AGP Accelerated Graphics Port - An interface specification from INTEL that enables 3D-graphics to display very fast. AGP is based on PCI, but is designed especially for the high throughput requirements of 3D-graphics. AHDL a) Altera (specific) Hardware Description Language - vendor specific HDL b) Analog Hardware Description Language - for analog designs/systems AIM Advanced Interconnect Matrix - vendor specific name for a CPLD switch-matrix (XILINX, e.g. CoolrunnerII-family) Aliasing is a distortion-producing reflection caused by the fact that all frequency components higher than half the sampling-frequency are reflected in the lower range. (To avoid, a low-pass filter is required, Anti-Aliasing) ALM Adaptive Logic Module - vendor specific name for a coarse-grained FPGA logic-module (e.g. Altera StratixII) ALSI Analog Large Scale Integration - complex analog chip design AMPP Altera Megafunction Partners Program - A program that was established in 1995 to bring the advantage of megafunction (IP) to Altera PLD users. Anti-Aliasing is a procedure to avoid aliasing Antifuse Opposite of a 'fuse', where a link is grown (not blown) to make a ellectrically connection by passing current through (see also technology-guide @ FPGA-guide.com) APU Altera Programming Unit ASIC Application Specific Integrated Circuit - A custom or semicustom integrated circuit, such as a cell or gate array, created for a specific application. ASMBL Advanced Silicon Modular Block - column based PLD-architecture which was introduced by Xilinx with the Virtex-4 device-family ASSP Application Specific Standard Part - integrated circuit (IC) for standard application (e.g. 74xx-series standard logic products) ATA Advanced Technology Attachment - a disk drive interface standard for IDE (Integrated Drive Electronics) ATPG Automatic Test Pattern Generator  B Backannotation typically means to write back the calculated propagation delays after the place&route-process for a post-layout simulation (standard format : SDF) BC Best Conditions for a timing-logic-simulation reflects 1.) max. supply-voltage 2.) min. temperature 3.) best technology process (typ. for hold-time violation check) BCD BCD - ...... BFM Big Fast Megablock - part of a vendor-specific CPLD-architecture with a distributed switch-matrix (LATTICE, e.g. ispLSI8000V-family) BGA Ball Grid Array - type of chip connection/packaging methodology (see also package-guide @ FPGA-guide.com) BIST Build-In Self Test - additional on-chip circuitry for an self-test Boundary Scan is a methodology allowing complete controllability and observability of the boundary pins of a JTAG compatible device via software control. This capability enables in-circuit testing without the need of bed-of-nail in-circuit test equipment. (sometimes abbreviated with BST) BPPG Boundary-Scan PLD Programming Generator - JTAG trademark (see also IEEE 1532) BPSK Bi-Phase Shift Keying - is a digital frequency modulation technique used for sending data over a coaxial cable network. BQFP Bumpered Quad Flat Pack - type of chip connection/packaging methodology (see also package-guide @ FPGA-guide.com) BRAM a) Buffer RAM (AT&T) b) Block RAM (XILINX) Breadboard is used to assemble preliminary circuits and parts to prove the feasibility of a device, circuit or system without regard to the final configuration or packaging of the parts. BSDL Boundary Scan Description Language - language to describe the Boundary Scan behavior of a device BST Boundary Scan Test - see also "Boundary Scan"  C CAE Computer Aided Engineering - computer aided engineering tools to develop something CAD Computer Aided Design - computer aided design tools to develop something CAM Content Addressable Memory - is a kind of storage device that includes comparison logic with each bit of storage. A data value is broadcasted to all words of storage and compared with the values therein. Words that match are flagged. (Also known as "associative memory") CBGA Ceramic Ball Grid Array - type of chip connection/packaging methodology (see also package-guide @ FPGA-guide.com) CCC Clock Conditioning Circuit - vendor specific name for a embedded on-chip clock-module with integrated PLL for de-skew, multiply, phase-shifting, ... (e.g. ACTEL ProASIC3) CDIP Ceramic Dual In-Line Package - type of chip connection/packaging methodology (see also package-guide @ FPGA-guide.com) CDR Clock Data Recovery - procedure to recover clock and data from a serial bitstream CFB Configurable Function Block - vendor specific name for a FPGA logic-module (INTEL, e.g. FLEXlogic-family) CFI Common Flash Memory Interface - vendor interface-standard for flash memories CFM Configuration Flash Memory - vendor specific name for a on-chip configuration memory on volatile PLDs, for automatic configuration after power-on (e.g. ALTERA MAX2-devices) CLB Configurable Logic Block - vendor specific name for a coarse-grained FPGA logic-module (XILINX-devices) CLCC Ceramic J-Leaded Chip Carrier - type of chip connection/packaging methodology (see also package-guide @ FPGA-guide.com) CLE Configurable Logic Element - vendor specific name for a small logic-unit (LUT+FF) of a coarse-grained FPGA logic-module (LATTICE-devices) CLK CLocK - a global net/signal which is the heartbeat of all digital synchronous designs/circuits. CMOS Complementary Metal-Oxide-Semiconductor - technology with two complementary unipolar (N-MOS and P-MOS) Field-Effect-Transistors (FET) Codec COmpressor / DECompressor - any technology for compressing and decompressing data. CPGA Ceramic Pin Grid Array - type of chip connection/packaging methodology (see also package-guide @ FPGA-guide.com) CPLD Complex Programmable Logic Device - PLD architecture type (see also architecture-guide @ FPGA-guide.com) CQFP Ceramic Quad Flat Pack - type of chip connection/packaging methodology (see also package-guide @ FPGA-guide.com) CRC Cyclic Redundancy Check - procedure to prevent errors at data transmissions by adding a measure of redundancy to data CSBGA Chip Scale Ball Grid Array - type of chip connection/packaging methodology (see also package-guide @ FPGA-guide.com) CSoC Configurable System-on-Chip CSOP Ceramic Small-Outline Package - type of chip connection/packaging methodology (see also package-guide @ FPGA-guide.com) CSP Chip Scale Package - type of chip connection/packaging methodology (see also package-guide @ FPGA-guide.com) CSSP Customer Specific Standard Product - a ASSP with a customizeable part on the same chip, introduced by Quicklogic (known CSSP-families : PolarPro, ArticLink) CuPL CuPL - is a description language for programmable logic (PLDs)  D DAC Digital-to-Analog Converter DCM Digital Clock Manager - vendor specific name for a embedded on-chip clock-module for de-skew, multiply, phase-shifting, ... (e.g. XILINX Virtex-II) DCI Digitally Controlled Impedance - of an output (e.g. XILINX Virtex-II) DCS Dynamic Clock Select - vendor specific name for a special clock-multiplexer (e.g. LATTICE ECP/EC-family) DDR Double Data Rate - property of a device, that works on both clock-edges (e.g. DDR-SDRAM) DES Data Encryption Standard - transmission procedure for security applications DFS Digital Frequency Synthesizer Die Die - name for the small silicon plate inside a chip DIP (DIL) Dual In-Line Package - type of chip connection/packaging methodology (see also package-guide @ FPGA-guide.com) DLL Delay Locked Loop - digital circuitry for frequency multiply, phase-shift, ... (similar analog PLL) DMA Direct Memory Access/Addressing - is a method of transferring data from one memory area to another without having to go through the central processing unit. DPA Dynamic Phase Alignment - PLL-core feature of e.g. Altera StratixGX FPGAs DPS Digital Phase Shifter DRAM Dynamic RAM - volatile read/write memory, content only stable for some milliseconds, refreshcycles required DRC Design Rule Check DSP Digital Signal Processor - device or module to process analog signals which have been converted to digital form (audio, video, ...).  E EAB Embedded Array Block - vendor specific name for embedded on-chip RAM structures (ALTERA e.g. ACEX-1K-family) EBR Embedded Block RAM - vendor specific name for embedded on-chip RAM structures (LATTICE e.g. ispXPGA-family) ECU Embedded Computational Unit - vendor specific name for a embedded on-chip DSP-module with an integrated multiplier (e.g. Quicklogic QuickDSP-family) EDA Electronic Design Automation - Application Software tools for the development of integrated circuits and systems EDIF Electronic Data Interchange Format - vendor-independent common industry-standard format for electronic design-data/netlist EEPROM Electrically Erasable PROM - ellectrically erasable PROM EEPLD Electrically Erasable PLD EIA Electronic Industry Association ELA Embedded Logic Analyzer EPAC Electrically Programmable Analog Circuit - analog counterpart to FPGA (vendor:IMP) EPGA Embedded Programmable Gate Array - scalable reprogrammable embedded IP-Core for ASICs or ASSPs ("soft-hardware-core") (e.g. ACTEL Varicore) EPROM Erasable PROM - by UV-light erasable PROM, normally in a windowed package EPLD Electrically PLD ESB Embedded System Block - vendor specific name for flexible embedded on-chip RAM structures (ALTERA e.g. APEX-II-family) ESP Embedded Standard Product - a device that consist of pre-determined functions customized and supported by user-configurable logic (FPGAs) on the same piece of silicon.  F Fan In Fan In - is a term, that defines the input-load of the affected input, typically '1' (see "Fan Out"). Fan Out Fan Out - is a term, that defines the maximum number of digital inputs (Fan In) which can be driven by the affected output. FBGA Fine Pitch (Fine-Line) Ball Grid Array - type of chip connection/packaging methodology (see also package-guide @ FPGA-guide.com) FCBGA Fine Pitch Ceramic Ball Grid Array - type of chip connection/packaging methodology (see also package-guide @ FPGA-guide.com) FCRAM Fast Cycle RAM FDIP Windowed Frit Seal Dual In-Line Package - type of chip connection/packaging methodology (see also package-guide @ FPGA-guide.com) FEC Forward Error Correction - (algorithm) a class of methods for controlling errors in a one-way communication system. FEC sends extra information along with the data, which can be used by the receiver to check and correct the data. FEPROM Flash Erasable PROM - see "FLASH" FET Field Effect Transistor FFT Fast Fourier Transform - An algorithm for computing the "Fourier transform" of a set of discret data values given for a finite set of data points. FIFO First-In First-Out - type of memory management FIR Finite Impulse Response - methodology of a digital filter FLASH Flash - abbreviation of "Flash EPROM", like an EEPROM but faster ellectrically erasable (whole chip at one time) FLEX Flexible Logic Element MatriX - FPGA productname of ALTERA (e.g. FLEX8000, FLEX10K) Flip Chip Flip Chip Ball Grid Array - type of chip connection/packaging methodology (see also package-guide @ FPGA-guide.com) Flip-Flop is a basic digital logic circuit that can storage two states (high and low) controlled by an edge-triggered input FMBGA Fine Pitch Metall Ball Grid Array - type of chip connection/packaging methodology (see also package-guide @ FPGA-guide.com) FPBGA Fine Pitch Plastic Ball Grid Array - type of chip connection/packaging methodology (see also package-guide @ FPGA-guide.com) FPIC Field Programmable InterConnect - a IC with a big programmable interconnect matrix, and typically many I/O-pins to connect other ICs (e.g. LATTICE ispGDX-family) FPGA Field Programmable Gate Array - PLD architecture type (see also architecture-guide @ FPGA-guide.com) FPLA Field Programmable Logic Array - CPLD-like devices with programmable AND/OR matrix (SIGNETICS Corporation or National Semiconductors MAPL-family) FPSC Field Programmable System Chip - vendor specific name for an FPGA combined with an ASIC-part for special applications (e.g. LATTICE ORCA-family with onchip SERDES, PCI-cores, ...) FPSLIC Field Programmable System Level Integrated Circuit - ATMEL trademark for SOPC-features (e.g. ATMEL AT94-family) FSK Frequency Shift Keying - the use of frequency modulation to transmit digital data. (i.e. two different carrier frequencies are used to represent '0' and '1') FSM Finite State Machine - a very important circuitry to realize timing-driven tasks in realtime. The three basic FSM-types are : 1.) Medvedev 2.) Moore 3.) Mealy FTBGA Fine Pitch Thin Ball Grid Array - type of chip connection/packaging methodology (see also package-guide @ FPGA-guide.com) FZP Fast Zero Power - very low power CMOS technology developed by PHILIPS  G GAL Generic Array Logic - PLD device with SPLD-architecture and with programmable AND-matrix and fix OR-matrix (LATTICE) Gate a) basic element to perform logical functions, like a digital switch that can be turned open or closed depending on the input signals (min. two) b) control input of an Field-Effect-Transistor (FET) GLB Generic Logic Block - vendor specific name for a CPLD logic-block (LATTICE, e.g. pLSI1000,pLSI2000-family) Glue Logic a generic term for any interface logic or protocol that connects two component blocks. Hardware designers call anything used to connect LSI or circuit blocks "glue logic". GRM General Routing Matrix - vendor specific name for a special programmable logic-module interconnect of a FPGA (XILINX, e.g. XC5200-devices) GRP Global Routing Pool - vendor specific name for a CPLD switch-matrix (LATTICE, e.g. pLSI1000,pLSI2000-family) GTL Gunning Transceiver Logic - is a standard for electric signals in CMOS circuits that is used to provide high data transfer speeds with small voltage swings.  H HAL Hard Array Logic - hardwired/masked PAL-device HDL Hardware Description Language - a kind of language used for the conceptual design of integrated circuits (i.e. VHDL and Verilog). hold time - is the succeeding time value, typically for a register (D-FlipFlop), to avoid metastability after a data-transfer into the register-cell (see also "setup time") HQFP Heat-Sink Quad Flat Pack - type of chip connection/packaging methodology (see also package-guide @ FPGA-guide.com) HSOP Heat-Sink Small-Outline Package - type of chip connection/packaging methodology (see also package-guide @ FPGA-guide.com) HSSOP Heat-Sink Shrink Small-Outline Package - type of chip connection/packaging methodology (see also package-guide @ FPGA-guide.com) HTSSOP Heat-Sink Thin Shrink Small-Outline Package - type of chip connection/packaging methodology (see also package-guide @ FPGA-guide.com) HSTL High Speed Transceiver Logic - a high speed interface standard (JEDEC standard EIA/JESD8-6)  I IBA Integrated Bus Analyzer - on-chip debugging tool ICR In-Circuit Reconfigurability - possibility to reconfigure a device, which is PCB-mounted ILA Integrated Logic Analyzer - on-chip debugging tool IP Intellectual Property - a IP-core is a hardwired or soft-based (sourcecode or netlist) reusable circuitry that can be implemented in a new chip design ISP In System Programmable - property of a device, that is in-system programmable  J JTAG Joint Test Action Group - a standard specifying how to control and monitor the pins of compliant devices on a circuit board. Created in 1993. (IEEE standard 1149.1 and 1532 ) JEDEC The Joint Electron Device Engineering Council was originally created in 1960 as a joint activity between EIA an NEMA, to cover the standardization of discrete semiconductor devices and later expanded in 1970 to include integrated circuits. www.jedec.org  K  L LAB Logic Array Block - vendor specific name for a CPLD logic-block or a FPGA logic-module (ALTERA) Latch is a basic digital logic circuit that can storage two states (high and low) controlled by an level-triggered input Latch-Up Effect ...... LC Logic Cells - vendor specific name for a small logic-unit (LUT+FF) of a FPGA logic-module (XILINX-devices) LCA Logic Cell Array - vendor specific name for a FPGA-family (XILINX e.g. XC2000,XC3000,XC4000,...) LCC Logic Control Cell - vendor specific name for a macrocell (ICT, PEEL-devices) LE Logic Element - vendor specific name for a small logic-unit (LUT+FF) of a coarse-grained FPGA logic-module (ALTERA-devices) LFSR Linear Feedback Shift Register - usually used for generating sequences for scrambling / descrambling methods LIM Local Interconnect Matrix - vendor specific name for a special interconnect matrix inside a FPGA logic-module (XILINX, e.g. XC5200 devices) LM Logic Module - vendor specific name for a fine-grained FPGA logic-module, subdivided into 'register-cells' and 'combinatorial-cells' (ACTEL-devices) LPGA Laser Personalized Gate Array (vendor i.e. Chip Express) LPLD Laser Processed Logic Device - trademark of Clear Logic LPM Library of Parameterized Modules - library of customizable basic functions (multiply, shift, ...) for usage in PLD-design process (forced by ALTERA) LQFP Low Profile Quad Flat Pack - type of chip connection/packaging methodology (see also package-guide @ FPGA-guide.com) LSB Least Significant Bit LSI Large Scale Integration - vendor specific name for a CPLD-series (LATTICE e.g. pLSIxxxx, ispLSIxxxx,...) LUT Look-Up Table - an array or matrix of fix (complex) data-values that can be read out (very fast) by addressing them through input data-values LVCMOS Low Voltage CMOS LVDS Low Voltage Differential Signaling - low-power & low-noise differential signaling technology for high speed transmission LVPECL Low Voltage Positive Emitter Coupled Logic - low-voltage PECL LVTTL Low Voltage Transistor-Transistor Logic  M MAX Multiple Array matriX - CPLD productname of ALTERA's EPLD-family (MAX5xxx,MAX7xxx) MAPLD Military and Aerospace Applications of PLDs MBGA Metall Ball Grid Array - type of chip connection/packaging methodology (see also package-guide @ FPGA-guide.com) MCP Multi Chip Package - package with two or more dies inside MDIP Molded Dual In-Line Package - type of chip connection/packaging methodology (see also package-guide @ FPGA-guide.com) MFB Multi Function Block - vendor specific embedded PLD memory-structure (LATTICE, ispXPLD-family) MIPS Million Instructions Per Second - Indicator for computing performance MOSFET Metal Oxide Semiconductor Field Effect Transistor - is a transistor in which the conducting channel is insulated from the gate terminal by a layer of oxide. Therefore, it does not conduct even if a reverse voltage is applied to the gate. MPAC Mask Programmable Analog Circuit - hardwired EPAC (vendor:IMP) MPGA Mask Programmable Gate Array MPI Microprocessor Interface MPLD Mask-Programmed Logic Devices - masked versions of programmable logic devices MQFP Metal Quad Flat Pack - type of chip connection/packaging methodology (see also package-guide @ FPGA-guide.com) MSB Most Significant Bit MSOP Mini Small-Outline Package - type of chip connection/packaging methodology (see also package-guide @ FPGA-guide.com)  N NEPP NASA Electronic Parts & Packaging N-MOS N-MOS - abbreviation of N-channel MOSFET (see also "CMOS" and "P-MOS" NRE Non-Recurring Engineering costs - e.g.: the costs to design and manufacture the process-masks for an ASIC are NRE-costs  O ORCA Optimized Reconfigurable Cell Array - vendor specific name for a FPGA-family of LATTICE (formerly FPGA-family of AT&T) OCM On-Chip Memory ORP Output Routing Pool - vendor specific name for a special CPLD output switch-matrix (LATTICE, e.g. pLSI1000,pLSI2000-family) OTP One Time Programmable - property of a device which is not reprogrammable or erasable  P PAL Programmable Array Logic - PLD with a so called SPLD- or PAL-architecture with programmable AND-matrix and fix OR-matrix (first vendor was Monolithic Memories) PAR Place-And-Route PALASM - is an early hardware description language (HDL), used for PAL-devices introduced by Monolithic Memories (MMI). Developed by John Birkner in the early 1980s. PBGA Plastic Ball Grid Array - type of chip connection/packaging methodology (see also package-guide @ FPGA-guide.com) PCB Printed Circuit Board PDIP Plastic Dual In-Line Package - type of chip connection/packaging methodology (see also package-guide @ FPGA-guide.com) PCI Peripheral Component Interconnect - a personal computer loacl bus designed by intel PECL Positive Emitter Coupled Logic - a high speed interface standard PEEL Programmable Electrical Erasable Logic - a PEEL-array is a special kind of a PLD with FPGA-like routing-channels and PLA-like macrocells (vendor:ICT) PFF Programmable Function Unit (PFU) without RAM-functionality (vendor specific name for a FPGA logic-module, e.g. LATTICE XP-series) PFU Programmable Function Unit - vendor specific name for a coarse-grained FPGA logic-module to build logic,arithmetic,RAM or ROM (LATTICE, ORCA-series) PGA Pin Grid Array - type of chip connection/packaging methodology (see also package-guide @ FPGA-guide.com) PIA Programmable Interconnect Array - vendor specific name for a CPLD switch-matrix (ALTERA, e.g. MAX5000,MAX7000-family) PIC Programmable Input/Output Cell - vendor specific name for a programmable FPGA I/O-pad (LATTICE, e.g. ORCA series) PIP Programmable Interconnect Point - to program a link between two crossing nets PLA Programmable Logic Array - PLD device with SPLD-architecture, where the AND- and OR-matrix is programmable PLC Programmable Logic Cell - vendor specific name for a coarse-grained FPGA logic-module (LATTICE, e.g. ORCA series) PLCC Plastic J-Leaded Chip Carrier - type of chip connection/packaging methodology (see also package-guide @ FPGA-guide.com) PLD Programmable Logic Device - topic term for all SPLDs, CPLDs and FPGAs. PLICE Antifuse-technology from ACTEL (e.g. ACT-family) PLL Phase Locked Loop - analog circuitry to multiply/divide frequencies phase-locked PLS Programmable Logic Sequencer P-MOS P-MOS - abbreviation of P-channel MOSFET (see also "CMOS" and "N-MOS" PPGA Plastic Pin Grid Array - type of chip connection/packaging methodology (see also package-guide @ FPGA-guide.com) PQFP Plastic Quad Flat Pack - type of chip connection/packaging methodology (see also package-guide @ FPGA-guide.com) PREP PRogrammable Electronics Performance Corporation - organization founded in 1992 to specify benchmarks for programmable logic devices PROM Programmable ROM - on-time programmable (OTP) memory PSG Programmable Sequence Generator PTSA Product Term Sharing Array - vendor specific name of a part inside a CPLD logic-block to share product-terms between macrocells (LATTICE, e.g. ispLSI1000-family)  Q QDR Quad Data Rate - known from QDR-SRAMs which have two independent DDR (double-data-rate) ports QML Qualified Manufacturer Listing  R RAM Random Access Memory - random read/write memory RLDRAM Reduced Latency DRAM - low latency high performance DRAM with SRAM-like random access (co-developed by Micron & Infineon) www.rldram.com Rocket I/O vendor specific name for a serial highspeed transceiver (SERDES) on-chip hardware core (Xilinx) ROM Read Only Memory - memory with fix content RQFP Plastic PoweR Quad Flat Pack - type of chip connection/packaging methodology (see also package-guide @ FPGA-guide.com) RST ReSeT - a global net/signal to (re)set a synchronous digital circuitry into a defined state. There are two kinds of reset, asynchronous or synchronous. RTL Register Transfer Level - ...... a kind of hardware description language used in describing the registers of a digital electronic system, and the way in which data is transferred between the registers.  S SDF Standard Delay Format - is an IEEE-standard for the representation and interpretation of timing data for use at any stage of an electronic design process, especially during timing simulations. SDT Schematic Design Tool SDRAM Synchronous DRAM - volatile memory with fast synchronous interface, content only stable for some milliseconds, refreshcycles required SDIP Shrink Dual In-Line Package - type of chip connection/packaging methodology (see also package-guide @ FPGA-guide.com) SERDES Serializer Deserializer - fast serial receiver/transmitter hardware setup time - is the preceding time value, typically for a register (D-FlipFlop), to avoid metastability before a data-transfer into the register-cell (see also "hold time") SLIC Supplemental Logic and Interconnect Cell - vendor specific name for a special prog. logic-module interconnect with supplemental logic (LATTICE, e.g. ORCA3 FPGAs) SMT Surface Mount Technology - for PCBs SoC System on Chip SOIC Small-Outline Integrated Circuit - type of chip connection/packaging methodology (see also package-guide @ FPGA-guide.com) SOJ Small-Outline Integrated Circuit with J-Leads - type of chip connection/packaging methodology (see also package-guide @ FPGA-guide.com) SOP Small-Outline Package - type of chip connection/packaging methodology (see also package-guide @ FPGA-guide.com) SOPC System On Programmable Chip - name for a PLD with high densities and embedded structures on one chip SPGA System Programmable Gate Array - vendor specific name of a planned, but never materialized FPGA-family from ACTEL in 1996 (SRAM-based ES-family) SPLD a) Simple PLD - PLD architecture-type (see also architecture-guide @ FPGA-guide.com) b) Segmented PLD - vendor specific name for a PLD with CPLD-architecture SQFP Shrink Quad Flat Pack - type of chip connection/packaging methodology (see also package-guide @ FPGA-guide.com) SRAM Static RAM - volatile memory (synchronous or asynchronous interfaces possible), content only stable at power-on SRP Segment Routing Pool - part of a segmented vendor-specific CPLD switch-matrix (LATTICE, e.g. ispMACH5000VG) SSOIC Shrink Small-Outline Integrated Circuit - type of chip connection/packaging methodology (see also package-guide @ FPGA-guide.com) SSOP Shrink Small-Outline Package - type of chip connection/packaging methodology (see also package-guide @ FPGA-guide.com) SSTL Solid State Track Link STA Static Timing Analysis - the calculation of the longest or critical pathes of a design, supported by CAD/CAE-tools  T TAP Test Access Port - i.e. for JTAG BST TC Typical Conditions for a timing-logic-simulation reflects 1.) typ. supply-voltage 2.) room-temperature 3.) nominal technology process TCL Tool Command Language - mainly used as a script file to control CAE-tools or give additional project informations, constraints or assignments TFR Transparent Field Reconfiguration - vendor-specific PLD-feature for in-field logic update while system operates (e.g. LATTICE MachXO) TQFP Thin Quad Flat Pack - type of chip connection/packaging methodology (see also package-guide @ FPGA-guide.com) TSOP Thin Small-Outline Package - type of chip connection/packaging methodology (see also package-guide @ FPGA-guide.com) TSSOP Thin Shrink Small-Outline Package - type of chip connection/packaging methodology (see also package-guide @ FPGA-guide.com)  U UBGA Ultra Fin-Line Ball Grid Array - type of chip connection/packaging methodology (see also package-guide @ FPGA-guide.com) UES User Electronic Signature - User specific signature, which can be programmed on the PLD (e.g. ATMEL ATF2500B or ACTEL ACT-families) UFM User Flash Memory - non-volatile onchip flash memory for user-data (e.g. ALTERA MAX2-devices) UIM Universal Interconnect Matrix - vendor specific name for a CPLD switch-matrix (XILINX, e.g. XC7200 / XC7300 CPLD-family 1993) ULSI Ultra Large Scale Integration - superlative of VLSI  V Verilog is a hardware description language for digital electronic design and gate-level-netlist VHDL VHSIC Hardware Description Language - standardized language for ASIC/PLD-designers (IEEE 1076) VHSIC Very High Speed Integrated Circuit ViaLink Antifuse-technology from QUICKLOGIC (e.g. pASIC-family) VLSI Very Large Scale Integration - the process of placing thousands of electronic components on a single chip. VQFP Very Thin Quad Flat Pack - type of chip connection/packaging methodology (see also package-guide @ FPGA-guide.com) VSOP Very Small-Outline Package - type of chip connection/packaging methodology (see also package-guide @ FPGA-guide.com) VST Verification and Simulation Tool  W WC Worst Conditions for a timing-logic-simulation reflects 1.) min. supply-voltage 2.) max. temperature 3.) worst technology process (typ. for setup-time violation check)  X XPGA eXpanded Programmable Gate Array - vendor specific name for a PLD with FPGA-architecture (Lattice ispXPGA) XPLA eXtended PLA - vendor specific name for a macrocell of a CPLD logic-block (XILINX, Coolrunner devices) XPLD eXpanded PLD - vendor specific name for a PLD with CPLD-architecture (Lattice ispXPLD 5000MX)  Y  Z ZBT Zero Bus Turnaround - is a synchronous SRAM architecture optimized for networking and telecommunications applications ZIA Zero-power Interconnect Array - vendor specific name for a low-power CPLD switch-matrix (PHILIPS, e.g. XPLA-family)