Preface

Programmable logic devices (PLDs) use different process technologies to build the memory cells used to program a device. Nearly all of the current available PLDs are based on an unipolar CMOS-process. Some few bipolar devices are also available, cause the bipolar Fuse-technology was the original programming technology of the first days. The CMOS-process technology for PLDs can be devided up into five sub-technologies (see technology-tree below). Every technology has its advantages and disadvantages regarding to reliability, power-up or programming behaviour.

EPROM-technology

Erasable Programmable Read-Only Memory

EPROM cells are non-volatile memory cells. Similar to the technology used in standard EPROM memory devices. EPROM cells are electrically programmed in a device programmer. EPROM-based devices are erasable using ultra-violet light (UV-light), if they are in a windowed package. EPROM-based devices in a standard package are only one-time programmable (OTP).

EEPROM-technology

Electrically-Erasable Programmable Read-Only Memory

EEPROM cells are non-volatile memory cells. An EEPROM memory cell is physically larger (about 3 times) than an EPROM cell, but offers the advantage of being erased electrically. Cause of this great advantage many vendors implemented the in-system programmable (ISP) capability .

Flash EPROM-technology

Flash Erasable Programmable Read-Only Memory

Flash EPROM cells are non-volatile memory cells. FLASH has the electrically-erasable benefits of EEPROM but a smaller physical cell size (about 50%). Most FLASH-based devices are in-system programmable (ISP).

SRAM-technology

Static Random Access Memory

Similar to the technology used in static RAM devices, but with a few modifications for maximum stability instead of read/write performance. Because SRAM-technology is volatile (the contents disappear after power-down) the devices have to be bootet (configured) after power-up. This makes the devices in-system programmable (ISP) and reconfigurable during operation mode. Most SRAM-based FPGAs can configure themselves automatically at power-up from an external or internal (on-chip) configuration ROM.

Antifuse-technology

Antifuse cells are non-volatile and only one-time programmable (OTP). Instead of breaking a metal connection by passing current through (like fuse-technology), a link is grown to make a connection. Antifuse-based devices are very good for high reliability applications, cause of their unlimited data-retention time. Antifuse cells are electrically programmed in a device programmer. There are different kinds of CMOS-based PLD-Antifuse-technologies known, like PLICE, ViaLink or MicroVia.

Fuse-technology

Fuse cells are non-volatile and only one-time programmable (OTP). Fuse-technology was the original programming technology for programmable logic. A fuse is a metal link that can be programmed (blown) by passing a current through. Fuse cells are electrically programmed in a device programmer.